Recently, for example, in the processor or the like, the increase of the heat generation and/or the power consumption become a large problem. Along with this problem, a lot of tools to detect the behavior of the average heat generation and/or average power consumption and carry out the visualization or automatic modification are proposed. However, as for the heat generation and/or power consumption, not only the average behavior but also the temporal and/or spatial maldistribution may be a large problem. For example, the momentary change of the power consumption causes a malfunction due to the noise and/or the voltage drop. In addition, the local heat generation may cause the thermal runaway and/or destruction because the cooling is not in time locally. Then, it is desired that the several benchmark tests are carried out at the chip design stage to identify when and where the large load occurs and the design and/or implementation are optimized so that the load is not maldistributed in terms of time and space.
On the other hand, because huge costs and very long time are required for the design change of the processor or the like, the investigation (e.g. the logical verification and analysis of the power consumption and heat generation) of the behavior in the processor or the like is carried out before actually making the chip. However, when the inside of the recent processor or the like including more than one billion transistors is investigated by the software simulation, the operation speed in the simulation does not reach several Hz although it is actually several GHz. Then, the tools to carry out hardware acceleration of the simulation are provided from a lot of vendors.
When such an accelerator is used, the signal waves in the chip are obtained as a simulation result at the speed as fast as about 10 thousand times of the software simulator. As schematically depicted in FIG. 28, when Wire A and Wire B are defined as input wirings of a logic circuit of an AND circuit and Wire C is defined as an output wiring of the AND circuit, a predetermined input pattern is inputted to such logic circuits in the accelerator and the signal waves of the Wire A, Wire B and Wire C are obtained as an observation result as depicted in the right of FIG. 28.
Here, the consumed power can be calculated by using the observed waves in the wirings (=the number of change times of signals), wiring capacities and capacitances of logic cells (e.g. AND and OR) connected to the wirings, according to the relation “power consumption is proportional to (wiring capacities+cell capacitances)*the number of change times of signals”. However, even if all of the operations of more than billion logic cells are presented to a designer as wave signals and/or consumed power values of the individual cells, it is impossible for the designer to review all data.
On the other hand, in order to optimize the power consumption of the chip, following things must be considered: (1) the reduction of the total power consumption and/or total heat generation (specifically, the optimization of the logic and/or the optimization of the implementation in order to decrease the average power consumption and/or the average heat generation of the entire chip (i.e. cell downsizing, factoring, pin swapping or the like)); and (2) the reduction of the maldistribution of the power consumption and heat generation (specifically, when a lot of cells, which have possibility that they simultaneously operate, and/or a lot of cells, which have high operational ratio, are disposed too closely, the maldistribution of the power consumption is caused. This causes the local voltage fluctuation and heat generation, and further becomes a cause of the malfunction. The optimization of the logic and/or implementation may be carried out in order to smooth this maldistribution. Namely, re-disposition of the cells, the change of the logic and the like are carried out.)
A lot of methods for reducing the total power consumption and total heat generation have been proposed. As tools to automatically optimize the power consumption, some products have been sold. In addition, some tools to present the designer with the behavior of the power consumption and/or heat generation and narrow points necessary for the design improvement have been proposed.
Moreover, some documents disclose, for example, a processing including (1) defining observation targets (extracting characteristic signals such as a clock gating signal, a chip enable signal and the like); (2) attaching observation circuits (attaching counter circuits and registers storing the counting result to wirings of the respective signals to be observed); (3) observing the counters (operating the logic with the counter circuits on the simulator); (4) detecting peaks (identifying characteristic points at which the large change in the operation is found from the counting results); (5) measuring operational ratio (gathering detailed signal waves at the detected points); and (6) displaying the results (calculating the consumed power values from the signal waves and implementation information (capacitances of the cells and/or wirings), and presenting the designer with the numeral results).
However, the aforementioned conventional arts can obtain information necessary to reduce the average operational power consumption. However, they cannot obtain information necessary to smooth the maldistribution. This is because (1) the data amount to be processed is too large to gather all data and (2) even if a large amount of data can be gathered, it cannot be presented for the designer in an appropriate mode.
A specific example of (1) is described. Here, it is assumed that data concerning how often modules A and B operate is independently gathered, for example. The result is depicted in FIG. 29. Namely, both of the modules A and B operate once until time 1. The modules A and B also operate once from the time 1 to time 2. Then, the average consumed power from time 0 to the time 1 is the same as the average consumed power from the time 1 to the time 2. However, when considering the local power consumption and heat generation, it is said that the load from the time 0 to the time 1 during which the modules A and B simultaneously operate is larger than the load from the time 1 to the time 2 during which the modules A and B separately operate. Namely, in order to smooth the maldistribution of the power consumption, it is required to identify when and how the plural modules (e.g. neighboring modules) simultaneously operate. However, because a lot of modules are incorporated into the chip, it is impractical to select all combinations of them.
This is because only the counters (including registers that holds the counted value as depicted in FIG. 31) that count the number of pluses are simply attached to the characteristic signal wirings such as the gating clock signal as depicted in FIG. 30. Specifically, it takes one to two seconds per one time and one register as overheads to read out the counted value from the 32-bit register, which is disposed on the accelerator and holds the counted value. Then, it takes 56 hours=0.2 million*1 second to read out the counted value once from 0.2 million registers distributedly disposed on the accelerator as depicted in FIG. 30. Thus, it is difficult for the conventional arts to gather the large amount of data.
In addition, when specifically describing about (2), even if all of the operational ratios for several hundred thousand or several million module combinations are gathered and they are presented by the simple enumeration of the numerical values or consumed power graph for each module, it is difficult for the designer to grasp all of them. Namely, the designer analyzes only several hundred modules at the most.
Therefore, in the conventional arts, there is no semiconductor circuit design support technique enabling to gather the observation data for a lot of observation points in the observation target circuit from the simulation accelerator within the practical time.
In addition, in the conventional arts, there is no semiconductor circuit design support technique enabling to present with a large amount of data gathered from the observation points in the observation target circuit in such a mode that the designer easily grasp them.